1. Field of the invention
The present invention relates to a non-volatile semiconductor memory device. In particular, the present invention relates to a non-volatile memory device which is capable of writing and erasing data in an FN--FN operation by applying only positive voltages, thereby eliminating the need for a negative voltage pump and reducing the area occupied on a semiconductor chip.
2. Description of the Related Art
In recent years, logic LSIs incorporating different types of memory devices, e.g., DRAMs and flash memories, have attracted much attention. Among others, flash memories are capable of electrical rewriting and retaining data even after the supply of power is terminated. Therefore, flash memories are often utilized for storing internal data (defined below) as well as storing programming codes.
Flash memories for storing internal data are used for storing data during the operation of a logic LSI. It is advantageous to configure such a memory so as to function on only one voltage supply level. Rewriting data stored in the flash memories based on only one voltage supply level requires the use of a step-up pump. Fortunately, this class of flash memories allow the incorporation of a step-up pump because such memories generally have a large capacity and therefore occupy a large area on the chip; against such a large chip area, the typical area occupied by a step-up pump would be substantially negligible.
On the other hand, flash memories for storing programming codes will perform a rewrite operation only at the time of updates (as required, for example, when updating a programming into a subsequent and improved version). Thus, this class of flash memories undergo only a small number of rewrite operations, and also have a small capacity. Since the memory cell array incorporated in such memories will occupy a relatively small area on the chip as compared to what would be occupied by a step-up pump, it may be impossible to incorporate a step-up pumps which is essential for realizing a configuration which uses only one voltage supply level (hereinafter referred to as a "single supply-level configuration").
For the above reason, it may not be preferable with flash memories for storing programming codes to adopt a single supply-level configuration based on a step-up pump. Rather, it may be preferable to adopt a two supply-level configuration by introducing a high voltage (which is required for rewriting) from outside the memory, in addition to a logic voltage.
There is a class of flash memories which employ an FN--FN operation for rewriting data. Such a flash memory provides the following advantages:
(1) the chip area of the non-volatile memory device can be reduced; and PA1 (2) since a minute current (called an "FN tunnel current") is used for rewriting data, a smaller power consumption can be attained than by performing rewrite operations based on channel hot electrons, which would require a large current and hence result in a large power consumption. PA1 (1) NOR type flash memories; PA1 (2) NAND type flash memories; PA1 (3) DINOR type flash memories; PA1 (4) AND type flash memories; PA1 (5) ACT (Asymmetrical Contactless Transistor) type (=virtual grounding type) flash memories; and PA1 (6) FLTOX type flash memories. PA1 (1) As illustrated in FIG. 19, the floating gate FGE has a complicated structure and therefore a large size. This makes it difficult to minimize the cell area. PA1 (2) It is necessary to ensure that drains 5E have a high withstand voltage because a high voltage will be applied thereto. This inevitably results in a large drain region and a large call area.
With reference to FIG. 4A, the structure of a conventional flash memory FM4 will be described. The flash memory FM4 includes a flash memory array 10A, a row decoder 111, a column decoder 112, and a power supply section 115. The power supply section 115 includes a regulator circuit 13 and a negative voltage pump 14. The regulator circuit 13 regulates a voltage Vpp, which is supplied from an external voltage source (not shown), to a voltage Vpd, which in turn is supplied to the column decoder 112. The negative voltage pump 14 converts the voltage Vpp supplied from the external voltage source (not shown) to a negative voltage Vneg, which in turn is supplied to the row decoder 111. The power supply section 115 supplies the voltage Vpp from the external voltage source to the row decoder 111. Thus, the negative voltage pump 14 in the power supply section 115 is a requirement for the conventional flash memory FM4 in order to enable supply of the negative voltage Vneg to the row decoder 111.
Below are several examples of representative flash memories which perform rewriting based on the FN-FN operation:
Next, the operation principle and problems of each of the above flash memories will be described.
It is to be understood that each of the flash memories described below has a "stack gate type" memory cell structure. As used herein, a "stack gate type", memory cell is defined as a memory cell which is composed essentially of one transistor, whereas a "split gate type" memory cell refers to a memory cell which is composed essentially of two transistors.
First, write, read, and erase operations for a memory cell M00D of the NOR type will be described with reference to FIGS. 12A to 12C.
With reference to FIG. 12A, a write operation occurs as follows. A voltage Vpp (e.g., 12 V) is applied to a control gate CGD while applying e.g., 6 V to a drain 5D and e.g., 0 V to a source 4D. As a result of applying these high voltages to the control gate CGD and the drain 5D, a current is allowed to flow through the memory cell M00D. At this time, some of the electrons flowing through the memory cell M00D are accelerated by a high-level electric field in the vicinity of the drain 5D so as to be injected into a floating gate FGD, which may be referred to as "injection of channel hot electrons".
With reference to FIG. 12D, an erase operation occurs as follows. Zero volts are applied to the control gate CGD while applying a floating potential to the drain 5D and Vpp (e.g., 12 V) to the source 4D. As a result, electrons are extracted from the floating gate FGD, thereby lowering the threshold value of the memory cell M00D.
A flash memory cell can enter either a state where its floating gate has excess electrons or a state where the floating gate does not have excess electrons. The potential of a floating gate having excess electrons becomes lower than that of a floating gate not having excess electrons. Since a lower potential of the floating gate ultimately requires a higher control gate voltage, a memory cell whose floating gate has excess electrons is said to have a "higher" threshold value.
With reference to FIG. 12C, a read operation occurs as follows. A voltage Vcc (e.g., 3 V) is applied to a control gate CGD while applying 1 V to the drain 5D and 0 V to the source 4D. If the selected memory cell M00D has a low threshold value, a current flows therethrough; if the selected memory cell M00D has a high threshold value, no current flows therethrough.
In an NOR type flash memory, the diffusion layer defining the source is required to have a high withstand voltage because, as described above, a high potential is applied to the source 4D during erasure of data. This in turn requires a deep diffusion, which prevents reduction of the cell area. This also results in the problem of large power consumption during writing.
Table 1 describes the respective voltages applied during writing, erasure, and reading to the NOR type flash memory cell M00D:
TABLE 1 ______________________________________ drain gate source ______________________________________ write 6 V 12 V 0 V erase F 0 V 12 V read 1 V 3 V 0 V ______________________________________ F: floating state
Next, the problems associated with NAND type flash memories will be described Due to their NAND array configuration, NAND type flash memories provide the advantage of reducing the chip area occupied by the array: however, they also have a disadvantage in that the array configuration necessitates a high capacitance associated with the bit lines, resulting in slow random access. Therefore, NAND type flash memories are not suitable for storing programming codes where high speed random access is required.
DINOR type flash memories, AND type flash memories, and ACT type flash memories are fundamentally based on the NOR array configuration, which allows for high speed random access. Hereinafter, the fundamental operation principles of these types of flash memories will be described.
First, a DINOR type flash memory is disclosed in "A 3 V single supply-level DINOR type flash memory", Journal of Institute of Electronics, Information and Communication Engineers of Japan, 1993 SDM93, p.15.
FIG. 1 illustrates the structure of a memory cell M00A of a DINOR type flash memory. FIG. 1 is also a general illustration of a flash memory M00A to which the present invention is applicable, as described later.
As shown in FIG. 1, a generally U-shaped n well 2A is formed on the surface of a substrate 1A. In the substrate 1A, a p well 3A is formed. Within the p well 3A, an n+ source 4A and an n+ drain 5A are formed. Upon the portion of the substrate 1A between the source 4A and the drain 5A, a floating gate FGA is formed, with a tunnel oxidation film 6A interposed therebetween. On the floating gate FGA, a control gate CGA is formed with an interlayer insulation film 7A interposed therebetween.
Next, the operation principles of DINOR type memories will be described.
With reference to FIG. 13A, a write operation occurs as follows in the DINOR type memory cell of FIG. 1. A reference voltage vss (e.g., 0 V) is applied to the p well 3A, while applying a negative voltage Vneg (e.g., -8 V) to the control gate CGA and a high positive voltage Vpd (e.g., 4 V) to the drain 5A. As a result, a high level electric field, is generated in a portion where the drain 5A overlays the floating gate FGA, so that electrons are extracted from the floating gate FGA. As a result, the threshold value is lowered (which may be between 0 V and 1.5 V).
With reference to FIG. 13B, an erase operation occurs as follows in the DINOR type memory cell of FIG. 1. Since a negative voltage Ven (e.g., -4 V) is applied to the source 4A, a negative voltage Ven (e.g., -4 V) is applied to the p well 3A so as to prevent a forward voltage from being applied between the substrate 1A and the source 4A. Furthermore, a high positive voltage Veg (e.g., 8 V) is applied to the control gate CGA so as to generate a high level electric field in the source 4A and a channel portion CHA. Electrons are injected into the floating gate FGA from all areas of the channel portion CHA, thereby increasing the threshold value (which may be e.g., 4 V).
With reference to FIG. 13C, a read operation occurs as follows in the DINOR type memory cell of FIG. 1. One volt is applied to the drain 5A and 3 V are applied to the control gate CGA, so as to allow a current to flow through the memory cell M00A. If the memory cell M00D is a "written" memory cell, i.e., has a low threshold value, a current flows therethrough; if the memory cell M00D has a high threshold value, no current flows therethrough. Thus, these states are sensed by a read circuit including sense amplifiers and other elements, whereby the stored data can be read.
Table 2 describes the respective voltages applied during writing, erasure, and reading to the DINOR type flash memory cell M00A:
TABLE 2 ______________________________________ drain gate source well ______________________________________ write 4 V -8 V F 0 V erase F 8 V -4 V -4 V read 1 V 3 V 0 V 0 V ______________________________________ F: floating state
Next, the above operations are described in more detail, with reference to the structure of a flash memory array 10A shown in FIG. 14. As shown in FIG. 14, the flash memory array 10A includes bit lines BL (BL0 to BLm+1) coupled to drains 5A of memory cells M (M00A to MnmA) in the illustrated manner and word lines WL (WL0 to WLn) coupled to control gates CGA, with the memory cells M being provided in a matrix so as to correspond to the respective intersections between the bit lines BL and the word lines WL. Sources 4A are coupled to a common source SL.
First, the write operation will be described. In a DINOR type flash memory, writing is simultaneously performed for a plurality of memory cells coupled to a single word line WL, whereby the writing speed is enhanced.
FIG. 15 illustrates a state where the respective voltages are applied to the DINOR type flash memory. As shown in FIG. 15, when writing data "1", "0", "1", . . . , "0" to the memory cells M00 to M0m. coupled to the word lines WL0, the selected word line WL0 is -at 8 V, and the unselected word lines WL1, WL2, . . . are at the reference voltage Vss (e.g., 0 V).
The bit lines BL have different voltages depending on the data. When the data to be written is "1", a write voltage 4 V is output to the bit line BL. When the data is "0", the reference voltage Vss (e.g., 0 V) is output to the bit line BL so as to prevent writing. As a result, only the memory cells corresponding to data "1" have their threshold values lowered through the above-described mechanism.
An erase operation occurs so as to erase all of the memory cells in the memory cell array shown in FIG. 14, Specifically, the bit lines BL are placed in a floating state, and -4 V is applied to the p wells 3A and the common source SL. By applying 8 V to all of the word lines WL, electrons are injected to the floating gate FGA through the above-described mechanism, thereby increasing the threshold values of the memory cells.
A read operation occurs by applying 3 V only to the selected word lines WL0 and 0 V to the unselected word lines WL1 to WLn. A current is allowed to flow through each memory cell M to be read by applying 1 V to the drain thereof and 0 V to the common source.
Next, the fundamental operation principles of an AND type flash memory will be described. An AND type flash memory is disclosed in "AND type cells for a 3 V single supply-level 64 Mbit flash memory", Journal of Institute of Electronics, Information and Communication Engineers of Japan, 1993 SDM93, p.37, as well as Japanese Laid-open Publication No. 6-77437.
The operations of the AND type flash memories are fundamentally the same as those of the aforementioned DINOR type flash memories. The following description will be directed only to the differences therebetween.
The structure of the AND type flash memories disclosed in the above literature does not adopt a double well structure, i.e., a structure in which a p well is provided in a region surrounded by an n well, because the disclosed technique does not apply a negative voltage to the drain during erasure (as described later), eliminating the need for a double well structure.
Table 3 describes the respective voltages applied during writing, erasure, and reading to an AND type flash memory:
TABLE 3 ______________________________________ drain gate source well ______________________________________ write 4 V -8 V F 0 V erase F 12 V F 0 V read 1 V 3 V 0 V 0 V ______________________________________ F: floating state
The write and read operations of the AND type flash memories are performed by similarly applying voltages as in the case of write and read operations of the aforementioned DINOR type flash memories. Therefore, the description thereof is omitted.
The erase operation is different from that of the DINOR type flash memories. FIG. 13D illustrates the mechanism of the erase operation for memory cells M00D in an AND type flash memory. As shown in FIG. 13D, the drain 5B and the source 4B are placed in a floating state and a positive voltage is applied to word lines WL so as to generate a high level electric field between a channel portion CHB and a floating gate FGB, whereby electrons are injected into the floating gate FGB. As a result, the threshold value of the memory cell is increased.
In the AND type flash memories disclosed in the above literature, the bit lines and the source lines are divided by means of selection transistors (not shown) in order to perform writing and erasure for each single word line. Erasure for a single word line occurs by applying a high positive voltage Vpp (e.g., 12 V) to the selected word line so that electrons are injected into the floating gate FGB as described above. By applying the high positive voltage Vpp (e.g., 12 V) to all of the word lines in the entire memory cell array, it is possible to erase all data in the entire memory array, as in the case of the DINOR type flash memories.
Next, the fundamental operation principles of an ACT type flash memory will be described. An ACT type flash memory is disclosed in "A New Cell Structure for Sub-quarter Micron High Density Flash Memory", IEDM Tech. Dig., p. 267 (1995).
The fundamental operations of the ACT type flash memories slightly differ from those of the DINOR type flash memories and the AND type flash memories because the ACT type flash memories employ a virtual grounding type array in order to reduce the chip area of the memory cell array.
FIG. 6 is a cross-sectional view showing a memory cell M00C in an ACT type flash memory. FIG. 6 is also a general illustration of a flash memory M00C to which the present invention is applicable, as described later.
As shown in FIG. 6, the impurity density of a source 4C and a drain 5C each has a different distribution in a region immediately underlying the floating gate FGC from that in the other regions. The component elements corresponding to those illustrated in FIG. 1 are denoted by the same reference numerals as used therein, with the description thereof omitted.
With reference to FIG. 16A, a write operation occurs as follows in the ACT type memory cell of FIG. 6. A negative voltage Vneg (e.g., -8 V) is applied to the control gate CGC while applying a high positive voltage Vpd (e.g., 4 V) to a high-density diffusion layer (denoted as n+) of the drain 5C. As a result, electrons are extracted through the mechanism shown in FIG. 16A, whereby the threshold value is lowered. Thus, date is written to the memory cell.
On the other hand, electrons are not extracted in the low density region (denoted as n-) of the source 4C responsive to the application of the positive voltage Vpd, so that the threshold value is not lowered. Thus, writing is prevented there.
Next, the write operation will be described in more detail with reference to FIG. 7, which illustrates the relationship between one memory cell and an adjoining memory cell. As can be seen from FIG. 7, each source 4C or drain 5C forming one diffusion layer (n+, n-) is shared by two adjoining memory calls M00C. That is, a diffusion layer (n+, n-) which serves as a drain 5C of one memory cell M00C serves as a source 4C of an adjoining memory cell M00C.
When data is written to one memory cell M00C, the positive voltage VPd (e.g., 4 V) is applied to the drain 5C, while Vpd or a voltage for preventing writing may be applied to the source 4C. In order to allow the write operation to this memory cell to occur when a voltage for preventing writing is applied to the source 4C, its associated diffusion layer (n+, n-) must be placed in a floating state.
With reference to FIG. 16B, an erase operation occurs as follows in the ACT type memory cell of FIG. 6. A negative voltage Vne (e.g., -4 V) is applied to the diffusion layer (source 4C or the drain 5C) and the p well 3C, while applying Veg (e.g., 8 V) to the control gate CGC. As a result, a high level electric field is generated between a channel portion CHC and the floating gate FGC, whereby electrons are injected into the floating gate FGC.
A read operation occurs as follows in the ACT type memory cell of FIG. 6. A voltage Vbs (e.g., 1 V) is applied to the drain 5C (or the source 4C) and Vcc (e.g., 3 V) is applied to the control gate CGC. Thus, a current is allowed to flow through the memory cell M00C, which is sensed to effect data reading.
Table 4 describes the respective voltages applied during writing, erasure, and reading to an ACT type flash memory:
TABLE 4 ______________________________________ drain gate well ______________________________________ write 4 V -8 V 0 V erase -4 V 8 V -4 V read 1 V 3 V 0 V ______________________________________ F: floating state
Next, these operations will be described in more detail with reference to FIG. 17, which illustrates the structure of a memory cell for use in an ACT type flash memory 10C. With respect to the memory cells disposed along the same word line WL in FIG. 17, one bit line BL is shared by two adjoining memory cells. For example, the bit line BL1 is coupled to both of the memory cells M00 and M01.
The write operation for this memory cell array will be described. As in the case of the aforementioned DINOR type flash memories and AND type flash memories, writing is simultaneously performed for a plurality of memory cells coupled to a single word line WL.
FIG. 17 shows the voltages applied to the respective nodes in the array in the case where the data to be written are "1", "0", "1", . . . , and "0". When writing to the memory cells M00 to M0m, which are coupled to the word line WL0, a voltage Vnn (eg., -8 v) is applied to the word line WL0, while the bit lines BL0, BL1, BL2, . . . , BLn are retained at, respectively, 4 V, a floating potential, 4 V, . . . , and a floating potential. Thus, the aforementioned data are written to the array.
In an erase operation, all of the memory cells in the memory cell array are to be erased by applying -4 V to all of the bit lines BL0 to BLm+1 and 8 V to all of the word lines WL0 to WLn. Thus, electrons are injected at the floating gate FGC through the aforementioned mechanism, thereby increasing the threshold value.
A read operation occurs as follows, by applying 3 V to selected word lines WL and 0 V to unselected word lines. Specifically, Vbs (e.g., 1 V) is applied to the drain of any memory cell to be read, while applying Vss (e.g., 0 V) to the source thereof, so that a current will flow through the memory cell. For example, the data stored in the memory cell M00C can be read by applying Vcc (e.g., 3 V) to the word line WL0: Vbs to the bit line BL0; and Vss to the bit line BL1.
Next, the fundamental operation principles of an FLTOX type flash memory will be described. FIG. 19 illustrates the structure of a memory cell M00E in an FLTOX type flash memory. In a surface layer of a substrate 1E, an n+ source 4E and an n+ drain 5E are formed. A floating gate FGE is formed with a field oxidation film 6E interposed therebetween. On the floating gate FGA, a control gate CGE is formed with an interlayer insulation film 7E interposed therebetween.
An FLTOX type flash memory having the above structure is disclosed in "16 kb Electrical Erasable Non-volatile Memory", IEEE ISSCC Dig. Tech. Pap; pp.152-153 (1980), for example.
An application of a flash memory having the above cell structure in a memory cell array 10E shown in FIG. 20 will be described. This type of flash memory does not have a double well structure, and the well and the substrate 1 are always maintained at the same potential, i.e., Vss (e.g., 0 V).
A write operation occurs as follows. A voltage Vss is applied to the control gate CGE, and Vpp (e.g., 12 V) is applied to the bit line BL when data "1" is to be written to the memory cell. As a result, a high level electric field is generated between a floating gate FGE and the drain 5E, whereby electrons are extracted at the floating gate FGE, lowering the threshold value.
When writing data "0" is to memory cell, a voltage Vinh (e.g., 6 V) is applied to the bit line BL. As a result, the electric field between the floating gate FGE and the drain 5E is reduced, whereby the threshold value is maintained at a high level.
In order to avoid so-called drain disturbance, Vinh is applied to the unselected word lines WL.
An erase operation occurs as follows. The voltage Vpp is applied to all of the word lines WL in the selected memory cell array, while applying 0 V to the bit lines BL and placing the source lines in a floating state. Thus, electrons are injected from the drain 5E side so as to increase the threshold value.
Table 5 describes the respective voltages applied during writing, erasure, and reading to an FLTOX type flash memory:
TABLE 5 ______________________________________ drain gate source well ______________________________________ write 12 V 0 V F 0 V erase 0 V 12 V F 0 V read 1 V 3 V 0 V 0 V ______________________________________ F: floating state
The aforementioned DINOR type flash memories, AND type flash memories, and ACT type flash memories, all of which function based on the FN--FN operation, utilize negative voltages for the write and erase operations in order to facilitate a single supply-level configuration Such negative voltages are generated in an internal negative voltage pump. In addition, these operations also require high positive voltages, which are also internally generated by using a step-up pump.
As described above, logic LSIs incorporating different kinds of flash memories for storing programming codes are designed to have a relatively small memory capacity. Therefore, it is difficult to use a step-up pump and/or a negative voltage pump, which would occupy large chip areas.
Moreover, the only externally suppliable voltage, which is needed in addition to a logic voltage, is a high voltage from an external high voltage source (which is required for rewriting). In other words, it is impossible to externally supply a negative voltage to the DINOR type flash memories, AND type flash memories, and ACT type flash memories.
The FLTOX flash memories have the following problems:
Thus, the FLTOX type flash memories require an even larger cell area than that required for ETOX type flash memories. Therefore, minimization of the cell area, which is supposed as an advantage associated with flash memories based on the FN--FN operation, cannot be adequately attained.